In performing a digital to analog conversion utilizing switched capacitors, a discontinuity which is typically referred to as offset error may occur when transitioning between positive and negative numbers. Offset errors are caused, in part, from voltage errors associated with a digital to analog converter (DAC) structure. Such offset errors are very undesirable for DACs utilized in speech applications because offset error may introduce harmonic frequencies that drastically affect the quality of sound. Other errors associated with a DAC structure, such as gain and nonlinearity errors, are not as critical in speech applications and may be compensated otherwise. However, a DAC structure which is insensitive to voltage errors resulting from parasitic capacitances is also very desirable. Typical capacitive digital to analog circuits utilize a structure having the disadvantage of using many capacitors which are weighted commonly as much as two hundred and fifty-six units to one unit. In such applications, capacitive matching errors are a common problem. In an attempt to reduce the number of capacitors, others have used what is commonly known as a "dividing capacitor" which is a capacitor connected in series between two groups of parallel connected capacitors to effectively reduce or divide the total capacitance. A "dividing" capacitor however adds an additional capacitor to the total number of capacitors and increases circuit size. Typical bipolarity digital to analog circuit structures also require an additional capacitor for converting the sign bit by a conventional method such as offset binary.